Matrox Supersight e2 HPC platform for imaging now available with the Intel Xeon processor 5600 series

Intel Xeon processor 5600 series uses 32nm process technology and up to six cores to enhance image processing performance
Matrox Supersight e2 Computer Platform HPC for imaging applications now available with Intel Xeon processor 5600 series in both quad-core and hex-core (six-core) versions. (PresseBox) (München, ) Matrox Imaging announced their system host boards (SHB), utilizing the latest Intel Xeon processor, 5600 series (formerly codenamed Westmere-EP), are now available for its high performance computing (HPC) platform, Matrox Supersight e2.

Intel Xeon processor 5600 series is based on the latest generation Intel microachitecture (codenamed Nehalem) using new 32nm process technology. The Intel Xeon processor 5600 series is available in both quad-core and hex-core (six-core) versions.

This is exciting news for high-throughput applications in industries such as semiconductor and wafer inspections. More cores per processor improves parallelism in multi-processing, which translates to performance gains for compute-bound operations of these applications.
In addition, the Intel Xeon processor 5600 series includes a 12MB shared L3 cache and connects to DDR3L-SDRAM running at up to 1333 MHz. This provides higher bandwidth and better memory performance for I/O-bound operations - a significant benefit for imaging applications.

About Matrox Supersight e2
Matrox Supersight e2 is a high-performance computing platform designed for imaging applications with an extremely high throughput. Leveraging multiple clusters of CPUs, GPUs and FPGAs, Matrox Supersight e2 provides an environment for considerable data and task-level parallel processing through a unique PCI Express (PCIe) x16 2.0 (Gen2) switch fabric. Applications for Matrox Supersight e2 are developed with the Matrox Imaging Library (MIL) and its Distributed MIL API. As MIL is supported on all Matrox Imaging hardware platforms, development on Matrox Supersight e2 is simplified and ensures the source code is portable across all devices, from nodes with 48 CPU cores and 4 FPGAs, to a node with 12 CPU cores, 1 FPGA and 6 GPUs, and everything in between.

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